HPC Asia 2018 will hold two workshops:
|Time||13:00 - 16:30, 31, Jan., 2018|
|Place||same venue of the conference|
IXPUG (The Intel Xeon Phi Users Group) is an active community for the Intel Xeon Phi many-core architecture processor made up of users from all over the world. IXPUG manages several conferences and workshops every year to share the knowledge and examples of systems and applications based on the Intel Xeon Phi processor series. Intel Xeon Phi is one of the most powerful general-purpose processor to support advanced high performance computing with its very high parallel performance. In 2017, two systems based on Intel Xeon Phi are ranked in top-10 of the TOP500 list; Cori at NERSC, LBNL (30PFLOPS peak) and Oakforest-PACS at JCAHPC (25PFLOPS peak).
In this workshop, we call for contributed papers on applications, systems, performance evaluation, etc., based on the systems using the Intel Xeon Phi processors. Since the processor is supporting a signficant portion of HPC activity in the world, this provides a great opportunity for all the users on many-core architecture processors and we can expect large potential audiences as well as many paper contributors. We also plan a keynote talk related to this processor family and its use for advanced research.
All the attendees of HPC Asia 2018 are quite welcome to join the workshop, not only as paper authors, but also as audiences to share this most advanced processor technology, application examples and performance tuning.
The workshop will focus on PGAS (Partitioned Global Address Space) programming model and experiences of the application using PGAS, and the implementation of compiler, runtime and applications.
Its goal is to bring together researchers working in the area of PGAS programming models to parallelize applications, and share the experience using PGAS models. The workshop focuses on PGAS programming languages, tools and libraries with the special focus on experience about the applications developed using this programming model. The workshop is open to any languages and libraries to enables PGAS models. The papers presented practical implementations, scalability and parallelization efficiency are foreseen.