Poster Session

HPC Asia 2022 Best Student Poster Award in Memory of Hiroshi Nakashima

Professor Hiroshi Nakashima (Kyoto University, Japan) suddenly passed away on October 6, 2021 by a terrible traffic accident. He was a member of the HPC Asia Steering Committee, and his death is a great loss to the HPC community in Japan, Asia and the world. According to his valuable support to the HPC Asia 2022, the organizing committee has decided to bear his name in the Best Student Poster Award of HPC Asia 2022 in recognition of his excellent achievements in research and education in the HPC Community. We would like everybody to respect his achievements and to share loving memories of him.

• Eligibility: a poster presenter who is the first author of the poster and a student in BS, MS, and Ph. D courses.
• Evaluation: member of the award committee will comprehensively evaluate the 1-page extended abstract, the poster draft, the oral presentation in Poster blitz, and the discussion through Poster session core time (both the presented research result and the presentation quality are evaluated; this is not research award but poster presentation award).
• 1st, 2nd, and 3rd Prize (basically one for each prize) are planned.

Award Winners

1st Prize (two winners)

• Ryota Kusakabe (The University of Tokyo)
  • Poster: [#105] "GPU-accelerated Multiphysics-based Seismic Wave Propagation Simulation and its Surrogate Model with Machine Learning" / Ryota Kusakabe (The University of Tokyo), Tsuyoshi Ichimura (The University of Tokyo), Kohei Fujita (The University of Tokyo), Muneo Hori (Japan Agency for Marine-Earth Science and Technology), Lalith Wijerathne (The University of Tokyo))
• Kazuki Furukawa (University of Tsukuba)
  • Poster: [#118] "Efficiency and Effectiveness Analysis of a Scratchpad Memory on FPGA and GPU for Diffuse Radiation Transfer Simulation" / Kazuki Furukawa (University of Tsukuba), Yoshiki Yamaguchi (University of Tsukuba), Kohji Yoshikawa (University of Tsukuba), Ryohei Kobayashi (University of Tsukuba), Norihisa Fujita (University of Tsukuba), Taisuke Boku (University of Tsukuba), Masayuki Umemura (University of Tsukuba))

2nd Prize

• Ryota Miyagi (Kyoto University)
  • Poster: [#129] "An FPGA Accelerator of Bayesian Network Structure Learning Using Parallel Calculation of Local Scores" / Ryota Miyagi (Kyoto University), Hideki Takase (The University of Tokyo))

3rd Prize

• Yen-Chen Chen (The University of Tokyo)
  • Poster: [#134] "Cascadic Parareal Method for Explicit Time-Marching Schemes" / Yen-Chen Chen (The University of Tokyo), Kengo Nakajima (The University of Tokyo))

Poster presentations

• Speakers with * (asterisk) at the beginning are eligible for the Student Poster Award. The winner will be announced at 12:10-12:30 "Awarding & Closing" on Day 3, Friday, January 14th.

[#102] Graph optimization algorithm for low-latency indirect network

• Authors: Masahiro Nakao (RIKEN R-CCS), Masaki Tsukamoto (Kansai University), Yoshiko Hanada (Kansai University), Keiji Yamamoto (RIKEN R-CCS)
• Abstract (click to expand):
  In a parallel computer system, it is expected to improve the performance of the whole system by introducing an indirect network with a small host-to-host average shortest path length (h-ASPL). To discuss such indirect networks in graph theory, the Order/Radix Problem (ORP) has been proposed. ORP is defined as finding a graph with a minimum h-ASPL satisfying a given number of hosts and radix of a switch. This paper proposes an optimization algorithm for ORP. As a feature of the proposed algorithm, the symmetry of the graph improves its solution search performance. We evaluate the performance of the proposed algorithm using the problems of Graph Golf, an international competition for ORP. The results show that the proposed algorithm can create graphs with smaller h-ASPL as the symmetry becomes larger.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#103] Implementation of Radio wave propagation loss calculation using RT core

• Authors: *Shinya Hashinoki (Nagoya University), Satoshi Ohshima (Nagoya University), Takahiro Katagiri (Nagoya University), Toru Nagai (Nagoya University)
• Abstract (click to expand):
  In recent years, GPUs have shown remarkable performance improvements and are used as computation accelerators in various fields. On the other hand, some recent GPUs are equipped with dedicated hardware that enables high-speed ray tracing processing, which was not possible in the past. Since ray tracing processing can be applied to applications other than image rendering, we are planning to use it in the field of computational science.
  In this study, we implemented the computation of radio propagation loss using the ray tracing acceleration hardware (RT core) of the NVIDIA Turing GPU architecture by using the NVIDIA OptiX 7 programming model. The performance of the execution was evaluated by comparing the multi-threaded execution on CPU using OpenMP and the parallel execution on GPU using OpenACC. As a result, when the number of iterations of ray tracing calculation in radio propagation loss calculation is expressed in two dimensions as the problem size, the implementation using RT cores was faster than the other implementations for all problem sizes. This indicates that RT cores can be expected to be fully effective in the field of scientific and technological computing. Although OptiX 7 accelerates ray tracing calculations using RT cores, the programs using OptiX 7 require specialized knowledge for coding because of the unique data structure and program flow. In the future, we need to tackle these issues and fill in the gaps between OptiX 7 and ordinary computational science codes.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#104] Feature analysis for selection of implementations in an accurate matrix-matrix multiplication library

• Authors: *Shota Aoki (Nagoya University), Takahiro Katagiri (Nagoya University), Satoshi Ohshima (Nagoya University), Toru Nagai (Nagoya University)
• Abstract (click to expand):
  In this study, we aim to develop a software auto-tuning (AT) mechanism with AI to reduce the man-hours required for performance tuning in the field of numerical computations. We show an example of explainability of a result by machine learning (ML) when ML is applied to a case study of performance parameter tuning on a library for verified numerical computations. We use dgemm and 11 implementations of sparse matrix operations on CPU or GPU for matrix-matrix multiplication (MMM) with Ozaki method, which is a numerical algorithm with splitting a MMM into multiple MMMs to obtain accurate computations. And we constructed a ML model to predict which implementation is the fastest. We explained the prediction results of a classifier using LIME. As a result, we have reasonable explanations as follows: (1) In the case of that the ML model predicts SpMV with CRS (multiple right-hand-sides, internal parallelism) on CPU is the fastest, high sparsity is analyzed as a positive factor by LIME. In fact, this implementation is often faster when the sparsity is high. (2) The large matrix size was also analyzed as a negative factor. In fact, when the matrix size is larger than 2500, SpMM with CRS on GPU is often the fastest.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#105] GPU-accelerated Multiphysics-based Seismic Wave Propagation Simulation and its Surrogate Model with Machine Learning

• Authors: *Ryota Kusakabe (The University of Tokyo), Tsuyoshi Ichimura (The University of Tokyo), Kohei Fujita (The University of Tokyo), Muneo Hori (Japan Agency for Marine-Earth Science and Technology), Lalith Wijerathne (The University of Tokyo)
• Ryota Kusakabe is the 1st Prize winner of the HPC Asia 2022 Best Student Poster Award in Memory of Hiroshi Nakashima
• Abstract (click to expand):
  Physics-based earthquake simulation is expected to contribute to estimation and mitigation of earthquake damage. However, its computational cost is huge, especially for three-dimensional domain. To overcome the cost, we have been developing a variety of methods for large-scale three-dimensional earthquake simulation using the finite element method. In this poster, the GPU-accelerated method for multiphysics seismic wave propagation simulation considering soil liquefaction is presented. By revising the domain partitioning method and adopting element reordering that consider the characteristics of the multiphysics problem, we developed an algorithm with high parallel efficiency which is suitable for GPU architecture. Also, a 21-bit floating point data type is used to reduce communication cost. The whole analysis is parallelized with MPI and OpenACC. Even though the target multiphysics simulation is complex and could be unstable, the developed method can stably perform it.
  In the performance measurement on a GPU-based supercomputer, the developed method was 10 times faster than the method that used only CPUs. The developed method carried out a 30,000-time-step simulation with an 89,146,716-DOF soil structure model using 13 compute nodes of the GPU-based supercomputer for 3.6 hours. When this simulation was performed on a CPU-based supercomputer, it took 14.6 hours with 128 compute nodes, indicating the developed method drastically reduces necessary computational resources. As a result of the simulation speedup, more simulation results can be obtained. With machine learning using the obtained results, we constructed a neural network surrogate model of earthquake simulation and enabled even faster evaluation of complex multiphysics earthquake response.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#106] Non-Invasive Voice Disorder Detection

• Authors: *Lim Kee Boon (Temasek Polytechnic), Gina Tan Ci En (Temasek Polytechnic), Muhammad Adam (Temasek Polytechnic)
• Abstract (click to expand):
  Dysphonia is an alteration of voice production due to a morphological or functional alteration of the pneumo-articulatory apparatus. Moreover, dysphonia affects great number of people, with about one third of adults suffering from this disorder at least once in their lifetime. The conventional method used to diagnose dysphonia is via the use of laryngoscopy. However, the laryngoscopy examination is an invasive procedure performed by an experienced laryngologist. Furthermore, the equipment required is costly and not commonly found in primary care units. The aim of this study is to provide an alternative approach, which is efficient and non-invasive. The project proposed to develop a computer aided diagnosis (CAD) system to classify pathological and healthy voices from voice signal using Multi-layer Perceptron (MLP) and Convolutional neural network (CNN). The 58 healthy and 150 pathological voice signals initially undergone noise removal and downsampled from 8000 Hz to 1000 Hz. This study experimented on both raw and preprocessed voice signals to separately train and test the baseline MLP and 1D CNN models of various layers. Further, the models employed model improvement methods, such as the callbacks, dropout and weight regularization, together with K-fold cross validation and confusion matrix. Overall, 1D CNN model of one layer with callbacks of patience=50 and weight regularization yielded the best validation accuracy of 82.76% and training accuracy of 68.97% at epoch 121.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#107] Non-Invasive Fetal Cardiac Arrhythmia Detection

• Authors: *Seck Miao Zhen Christabel (Temasek Polytechnic), Soe Moe Hnin Sett (Temasek Polytechnic), Muhammad Adam (Temasek Polytechnic)
• Abstract (click to expand):
  Fetal cardiac arrhythmias defined as any irregular fetal cardiac rhythm or regular rhythm at a rate outside the reference range of 100 to 200 beat per minute (bpm). Arrhythmias discovered in about 1% of fetuses with about 10% of these considered as potential sources of morbidity. Although most fetal arrhythmias are benign, some can cause fetal hydrops and lead to fetal death. This means that up to 1 fetus in 100 need their arrhythmias to be closely monitored and if indicated, treated in-utero using antiarrhythmic therapy. The invasive direct fetal electrocardiogram monitors the fetal heart rate variability. This involved inserting electrode into the woman’s cervix and attached it to the baby’s head. Conversely, non-invasive fetal electrocardiography (NI-FECG) has the possibility to offer some added clinical information to assist in detecting fetal distress, and thus it offers novel diagnostic possibilities for prenatal treatment to arrhythmic fetus. This project proposed to develop a computer aided diagnosis system to classify arrhythmic fetus and normal rhythm fetus from non-invasive fetal electrocardiography (NI-FECG) using Multi-Layer Perceptron (MLP) and 1-Dimensional Convolutional Neural Network (1D CNN). The FECG signals are pre-processed and segmented into length of four ECG beats each. The segmented FECG are used to trained and test the baseline MLP and 1D CNN models of various layers. Further, the models experimented on model improvement methods together with K-fold cross validation and confusion matrix. Overall, 1D CNN model of five layers (with callbacks of patience=30) yielded the best validation accuracy of 94.99%.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#108] Performance benchmark of the latest EigenExa on Fugaku

• Authors: Toshiyuki Imamura (RIKEN/R-CCS), Takeshi Terao (RIKEN/R-CCS), Takuya Ina (RIKEN/R-CCS), Yusuke Hirota (University of Fukui), Katsuhisa Ozaki (Shibaura Institute of Technology), Yuki Uchino (Shibaura Institute of Technology)
• Abstract (click to expand):
  Eigensolver is one of the strongly demanded tools in modern simulations. RIKEN has been developing high-performance and reliable eigensolvers since 2012 for the K computer, 2020 for the supercomputer Fugaku. EigenExa refers to the heart of our eigensolver project and the signature software for large-scale and highly parallel computations. We have just released version 2.11 in 2021 as a standard library on Fugaku, which employs the novel one-stage scheme. Also, the classical one-stage scheme is available as most of the state-of-the-art eigensolvers such as ScaLAPACK and ELPA. Furthermore, we are exploring the possibility of exploiting the advantages of precision-aware approaches in terms of computational performance and through the study of computational verification, accuracy refinement scheme, and mixed-precision methods. The poster presentation demonstrates the preliminary but remarkably huge performance benchmark on Fugaku up to 16,384 nodes and the future release plan in a new accuracy and reproducibility perspective.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#109] Data Access Pattern Analysis for dCache Storage System

• Authors: *Amanda Pereira (Drake University), Alex Sim (Lawrence Berkeley National Laboratory), John Wu (Lawrence Berkeley National Laboratory), Shinjae Yoo (Brookhaven National Laboratory), Hiro Ito (Brookhaven National Laboratory)
• Abstract (click to expand):
  dCache is a storage management system with disk space for temporary and permanent file storage and connectivity to a larger high performance storage system (HPSS) for additional file storage. Ideally, all files will be stored locally on the dCache disks when they need to be accessed. Analysis of past dataset access patterns for the files stored on dCache is necessary to determine how dataset popularity varies over time and what factors might affect the fluctuation. Findings suggest that datasets are generally accessed only a few days at a time with an inconsistent day to day popularity measurement, and therefore should only be stored locally for the few days that they are popular. Immediately following a period of popularity, files should be moved to HPSS for long term storage until they are needed again to increase the efficiency of dCache.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#110] CoToCoA: A Communication-Efficient Framework for Coupling Programs

• Authors: Takeshi Nanri (Kyushu University), Yuto Katoh (Tohoku University), Keiichiro Fukazawa (Kyoto University), Yohei Miyake (Kobe University), Kazuya Nakazawa (Kobe University)
• Abstract (click to expand):
  To construct complex software systems by coupling existing programs, there have been developed several tools. For example, preCICE provides interfaces for partitioned multi-physics simulations, while VisIT enables connection of its viewer program to the existing simulations to enable in-situ visualization. As more efficient framework, this poster introduces CoToCoA (Code-To-Code Adapter) which leverages high-performance interconnects by utilizing MPI as the basement layer, supports asynchronous data transfer among programs and enables coupling with minimum modification to existing programs.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#111] RDMA with Double Buffering for Adjacent Communication

• Authors: *Kota Yoshimoto (Kogakuin University), Akihiro Fujii (Kogakuin University), Teruo Tanaka (Kogakuin University)
• Abstract (click to expand):
  In large-scale scientific computing programs, parallelization by MPI communication is generally used. MPI is convenient because it can be executed on many computers. However, interprocess communication often becomes a bottleneck in highly parallel computers. There is an interface called RDMA (Remote Direct Memory Access) to reduce the delay caused by communication.
  In this research, we measured and compared the performance of MPI, RDMA, and RDMA with double buffering for adjacent communication. As a result, RDMA with double buffering was confirmed to improve speed by up to 30% compared to MPI. Therefore, RDMA with double buffering reduced synchronization and was the most efficient communication method of the three.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#112] Quantumized Graph Cuts in Portfolio Construction and Asset Selection

• Authors: Bernard Lee (HedgeSPA Limited), Anthony Constantinides (Imperial College London)
• Abstract (click to expand):
  This paper is concerned with two fundamental problems in investment science, namely the construction of a portfolio by segregating target assets into sectors representing a typical market index and the selection of target assets from each of those sectors. Problem 1 can be solved in the Graph Theory sense by cutting the set A of assets into two disjoint subsets to maximize the difference in a certain measure f(x_1, x_2, ..., x_n) of one subset {x_1, x_2, ..., x_n} where n<N to the same measure of the remaining subset of N-n elements. This problem, known as finding the "maximum graph cut" or Max-Cut from Graph Theory, sounds intuitively straightforward for a small number of exemplar assets, but its complexity can be prohibitive when applied to real-world, industrial-scale problems (e.g. 1.6X10^32 combinations by explicit sampling for 500 components in the S&P 500). Problem 2 can be solved similarly by segregating the factor set of each asset used in estimating expected returns into smarter subsets, so that the estimate of expected returns can eliminate the inefficient choice of similar factors based on both fundamental characteristics and statistical criteria. This paper presents some of the initial results and our next steps for high-performance computational simulations.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#113] A simplified AINV method based on nonzero element positions of a coefficient matrix

• Authors: *Kengo Suzuki (Hokkaido University), Takeshi Fukaya (Hokkaido University), Takeshi Iwashita (Hokkaido University)
• Abstract (click to expand):
  In the last few years, GPUs have been utilized to efficiently solve a linear system of equations by means of preconditioned Krylov subspace methods. To exploit the potential of GPUs for massive data processing, the preconditioner is desired to have a high degree of parallelism. Whereas incomplete factorization preconditioners, such as IC, ILU, involve forward/backward substitutions that are not preferable for implementation on GPUs, sparse approximate inverse (SAI) preconditioners are suited for GPUs because their preconditioning processes are performed by sparse matrix-vector multiplications. However, SAI algorithms tend to take more time than incomplete factorizations to construct the preconditioners. Therefore, it is desirable to speed up the preconditioner construction part of the SAI preconditioners. In this research, we focus on the AINV preconditioner. Simplifying some procedures of the AINV algorithm, we propose a new AINV variant. Experimental results show that the proposed algorithm is superior to the standard AINV algorithm.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#114] Parallelization of Automatic Tuning by Executing Machine Learning Programs in Multiple Jobs

• Authors: *Sorataro Fujika (Kogakuin University), Teruo Tanaka (Kogakuin University), Akihiro Fujii (Kogakuin University), Yuka Kato (Tokyo Woman's Christian University), Satoshi Ohshima (Nagoya University), Takahiro Katagiri (Nagoya University)
• Abstract (click to expand):
  We are working on the study of simultaneous estimation of multiple parameters by automatic tuning using iterative one-dimensional search, and this time we applied it to a machine learning program. This machine learning program is an application for pedestrian route prediction that takes about 5.5 hours for one actual measurement. This report shows that automatic tuning, which takes 35 days for sequential execution, can be completed in about 2.4 days by parallelizing.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#115] White-box Modelling of Parallel Computing Dynamics

• Authors: *Ayesha Afzal (Erlangen National High Performance Computing Center/Friedrich-Alexander University Erlangen-Nuernberg), Georg Hager (Erlangen National High Performance Computing Center/Friedrich-Alexander University Erlangen-Nuernberg), Gerhard Wellein (Erlangen National High Performance Computing Center/Friedrich-Alexander University Erlangen-Nuernberg)
• Abstract (click to expand):
  "White-box" performance modeling of distributed-memory applications is often inaccurate due to the wide spectrum of disturbances, which have a variety of performance impacts. Establishing a comprehensive theory of the underlying dynamics that destroy the "lock-step" pattern of bulk-synchronous parallel programs is a great challenge in HPC. As a first step, we have developed a validated analytic model of the propagation speed of "idle waves." Idle waves emerge when delays on individual MPI processes propagate across the others depending on the execution and communication properties of the program. We use a spectrum of HPC resources and application scenarios to further explore how these idle waves interact nonlinearly within a parallel code on a cluster and what are the key ingredients in their decay. A bottleneck among processes may break the inherent symmetry of the underlying software and hardware, leading to a structured, stable desynchronized state and an automatic communication and computation overlap. Although desynchronization can cause increased per-process waiting time, it can also boost the per-process memory bandwidth via bottleneck evasion, improving the overall time to solution. We have devised a performance model that can predict the memory bandwidth share per kernel on a memory contention domain depending on the number of active cores and the bandwidth characteristics of paired kernels. Our innovative modeling approach addresses the analysis and simulation challenges of the dynamics of parallel computing and connects them to the physical world via a coupled oscillator model serving as a high-level cluster characterization tool.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#116] IC(p) Preconditioning with Acceleration Factor for High-Frequency Electromagnetic Field Analysis

• Authors: Koki Masui (Osaka University), Masao Ogino (Daido University), Takahiro Katagiri (Nagoya University), Fumihiko Ino (Osaka University)
• Abstract (click to expand):
  Iterative methods suffer from oscillating residual norm histories and slow convergence rates in solving the complex symmetric linear equations derived from the edge finite element analysis of high-frequency electromagnetic fields. Although IC(p) can improve the convergence, there are few examples and an efficient implementation method has not been established in the past. Moreover, there is no example of applications for complex number problems such as electromagnetic field analysis. Therefore, we implement and optimize IC(p) that focuses on the position of non-zero elements in the coefficient matrix. As a result, our method succeeded in reducing both the number of iterations and the computation time and demonstrating its effectiveness in electromagnetic field analysis problems.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#117] A Weak Scalability Study of File Aggregation in Asynchronous, Multi-Level Checkpointing

• Authors: *Mikaila J. Gossman (Clemson University), Bogdan Nicolae (Argonne National Laboratory), Melissa C. Smith (Clemson University), Jon C. Calhoun (Clemson University)
• Abstract (click to expand):
  Checkpointing is a common and necessary task of many scientific applications, both for defensive purposes such as fault tolerance and productive ones, like job management or producer-consumer workflows. Traditionally, checkpointing has been done synchronously, meaning it blocks the application until all processes of a distributed system have completed checkpointing to a parallel file system (PFS). However, synchronous checkpointing methods are expected to be infeasible at Exascale, and thus application scientists have begun adopting asynchronous multi-level checkpointing algorithms. Asynchronous multi-level libraries checkpoint to fast, local storage first, then the application resumes and local checkpoints are flushed to the PFS concurrently. Current asynchronous, multi-level checkpoint algorithms, like VELOC adopt a file-per-process flush strategy, ensuring a simple, lock-free I/O implementation. However, file-per-process methods lead to many PFS files, making this type of write strategy suboptimal in the previously identified workflows. Therefore, checkpointing strategies must implement aggregation to facilitate management and usability. While aggregation is explored in the context of synchronous checkpointing, to our knowledge, it remains virtually unexplored in the context of asynchronous checkpointing. Further, asynchronous checkpointing creates competition between the application and checkpointing processes as both perform their tasks concurrently. Thus, implementing aggregation in asynchronous checkpointing algorithms is a nontrivial task involving co-design of aggregation and mitigation strategies. This work analyzes the impact of two introductory aggregation strategies on the checkpointing process through a targeted microbenchmark.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#118] Efficiency and Effectiveness Analysis of a Scratchpad Memory on FPGA and GPU for Diffuse Radiation Transfer Simulation

• Authors: *Kazuki Furukawa (University of Tsukuba), Yoshiki Yamaguchi (University of Tsukuba), Kohji Yoshikawa (University of Tsukuba), Ryohei Kobayashi (University of Tsukuba), Norihisa Fujita (University of Tsukuba), Taisuke Boku (University of Tsukuba), Masayuki Umemura (University of Tsukuba)
• Kazuki Furukawa is the 1st Prize winner of the HPC Asia 2022 Best Student Poster Award in Memory of Hiroshi Nakashima
• Abstract (click to expand):
  This paper proposes the efficient buffering approach for implementing radiative transfer equations to bridge the performance gap between processing and global memory bandwidth. The radiation transfer equation originally focuses on the fundamental physics process in astrophysics. Besides, it has become the focus of a lot of attention in recent years because of the wealth of applications such as medical bioimaging. However, the acceleration requires a complicated memory access pattern with low latency, and the earlier studies unveil conventional memory access based on software control has no aptitude for this computation.
  Thus, this article introduced an application-specific buffering scheme called PRISM (PRefetchable and Instantly accessible Scratchpad Memory) and apply it to a GPU and an FPGA. The proposed approach was compared between GPU and FPGA-based implementation. The results show that the original ART implementation can be improved by an FPGA using the PRISM when the simulation space is small and by a GPU when it is large. We prove that the buffering scheme reduces the memory access bottleneck and contributes to a significant increase in the arithmetic circuit utilization of the accelerators.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#119] FPGA Memory System for HPC Applications using Addressable Cache

• Authors: Norihisa Fujita (University of Tsukuba), Ryohei Kobayashi (University of Tsukuba), Yoshiki Yamaguchi (University of Tsukuba), Taisuke Boku (University of Tsukuba)
• Abstract (click to expand):
  In our previous work, we implemented an astrophysics application for the early universe for a Field Programmable Gate Array (FPGA) cluster. We conducted that FPGAs can run parallel applications efficiently thanks to their high-performance direct inter-FPGA communication. However, the memory bandwidth of an FPGA is the bottleneck to implementing an HPC application on it. The FPGA board used in the work has only 4 channels of DDR4 memory (76.8GB/s), whereas other accelerators have more than 1TB/s of memory bandwidth.
  Intel Stratix 10 MX FPGA has High Bandwidth Memory (HBM) 2 providing up to 512GB/s of memory bandwidth. HBM2 aggregates many slow memory channels to achieve high performance. Although an FPGA does not have a sophisticated memory network, it must handle all memory channels simultaneously to obtain maximum performance from HBM2 memory. This is a big challenge for FPGAs equipping HBM2 memory.
  We propose a new memory system for FPGA and HPC applications using addressable caches. We believe that automatic cache system like CPUs is not suitable for HPC FPGAs. If we use an automatic cache system that consumes a lot of resources, resources for the computation are reduced. These caches have data copy controllers to transfer data between caches and memories. We describe how to copy data explicitly because these caches are not automatic. Our system also has crossbars to maximize the performance and flexibility of data transfer from and to HBM2 memory. In this poster, we show the work-in-progress implementation and the performance evaluation of the proposed memory system.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#120] Performance Evaluation of the Mixed Precision GMRES(m) Method using FP64 and FP32

• Authors: *Yingqi Zhao (Hokkaido University), Takeshi Fukaya (Hokkaido University), Takeshi Iwashita (Hokkaido University)
• Abstract (click to expand):
  Traditionally, numerical methods using double precision floating-point number (FP64) are often considered to solve problems in linear algebra such as system of linear equations. However, due to the limitation of power budget, it becomes difficult to improve the performance of FP64. This situation makes it more and more necessary to develop a new method that can exploit low precision computing and provide computed results with the same accuracy as by traditional methods using only FP64.
  In this study, a mixed precision variant of the GMRES(m) method, which is one of widely-used iterative linear solvers, using FP64 and FP32 is discussed. Its numerical behavior is investigated in detail through numerical experiments with various test matrices. Compared with the traditional GMRES(m) method using FP64, the numerical results are analyzed from various aspects: the number of iterations, the achievable accuracy, and the execution time.
  From the results, several observations are obtained; for example, when the restart frequency m is small, the number of iterations of two methods are basically the same. However, when m increases, a different tendency is observed. Besides, there is almost no difference in the final achievable accuracy of the two methods. It is also confirmed that the mixed precision GMRES(m) has better performance than the traditional GMRES(m) method in terms of the execution time.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#121] Performance Measurement of a Hierarchical File System for Distributed Deep Neural Network Training

• Authors: Takaaki Fukai (RIKEN Center for Computational Science), Kento Sato (RIKEN Center for Computational Science)
• Abstract (click to expand):
  Today, deep learning is an essential technology for our life. To solve more complex problems with deep learning, both sizes of training datasets and neural networks are increasing. Therefore, distributed deep neural network (DDNN) training is necessary. For large scale DDNN training, HPC clusters are a promising computation environment. In large-scale DDNN, I/O performance is a critical matter because it is a bottleneck in some training workloads. For designing the storage systems of future HPC clusters, it is necessary to reveal the impact on the training performance of the difference in the storage system design.
  To reveal it, we study on the performance measurement and analysis of the hierarchical storage system for the DDNN training workload. We plan to evaluate the impact on the training performance by the difference in the throughput and volume size between the local file system and the global file system. In this poster presentation, we report the results of the preliminary experiments for the measurement. One of the preliminary experiments is for changing the throughput of the global file system. To achieve the different speed global file systems for evaluating the impact of throughput difference, we change its performance by changing the number of object storage targets~(OST). The results shows that we can change the throughput of the global file system even in the access pattern by controlling the number of OSTs.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#122] Memory-aware Task Mapping for Heterogeneous Multi-Core Systems

• Authors: *Yifan Jin (Tohoku University), Mulya Agung (The University of Edinburgh), Jiaheng Liu (Tohoku University), Hiroyuki Takizawa (Tohoku University)
• Abstract (click to expand):
  As a new trend in processor design, a multi-core processor has evolved to employ a heterogeneous multi-core architecture integrating some kinds of cores with different performance and energy characteristics on a single chip. In addition, the Non-Uniform Memory Access (NUMA) architecture has become a de facto standard in modern HPC systems. Because task mapping could significantly affect the usage of systems’ heterogeneity and memory resources, proper task mapping will be a key to high performance and energy efficiency. However, the conventional task mapping methods will no longer be suitable for the NUMA systems built with heterogeneous multi-core processors. Our work will deal with this problem by properly combining memory-aware task mapping and heterogeneity-aware task mapping. Considering the diversity of system configuration and application characteristics, this work proposes a mapping strategy, which includes two priority options, the memory-aware priority option and the heterogeneity-aware priority option, and a priority option switching mechanism. Choosing one of the priority options will prioritize the impact of that factor at the task mapping. Our proposed switching mechanism selects appropriate priority options for individual systems and applications considering their performance characteristics. Our evaluation results have shown that only one priority option cannot provide a suitable mapping for all kinds of applications. This shows the necessity of the two mapping priority options and the switching mechanism proposed in this work. Our work will also investigate the key performance characteristics of applications that can be used to determine the mapping priority.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#123] Multi-GPU computing of moving boundary flow using lattice Boltzmann method

• Authors: *Akira Hatakeyama (The University of Tokyo), Takashi Shimokawabe (The University of Tokyo)
• Abstract (click to expand):
  Moving boundary flow is the simulation of flow around objects moving freely, and it is one of important themes of computational fluid dynamics (CFD). We use immersed boundary-lattice Boltzmann method (IB-LBM) to solve moving boundary flow. Parallel computing using GPU makes the computing time of IB-LBM short, and using multiple GPUs does more. However, in multi-GPU computing, it is necessary to communicate data between GPUs, and it decreases parallel efficiency.
  We implement IB-LBM in three ways in order to increase parallel efficiency. One implementation is naive. In another implementation, we reduce amount of communication data, for example, considering the velocity direction of particles. In the other implementation, we hide communication time. CPU communicates data while GPU computes domain that is not related to communication. As a result, second implementation improve performance of IB-LBM, and third more.
  In addition, we evaluate performance of IB-LBM, changing the way to assign GPUs to subdomains when two dimension split. Split direction and whether GPUs are in same compute node affect communication time between the GPUs. Thus, we assign GPUs to subdomains properly, considering communication time of which direction we hide. By doing this, we improve performance of IB-LBM.
  In this poster, we provide the implementations of IB-LBM, and show the results of each implementation and how to assign GPUs.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#124] An FPGA-based Accelerator for Sound Field Rendering with High-order FDTD

• Authors: Yiyu Tan (RIKEN Center for Computational Science), Toshiyuki Imamura (RIKEN Center for Computational Science), Masaaki Kondo (RIKEN Center for Computational Science)
• Abstract (click to expand):
  Sound field rendering with FDTD method is computation- and memory-intensive. This research investigates FPGA-based acceleration on sound field rendering with high-order FDTD method, in which spatial and temporal blockings are applied to alleviate external memory bandwidth bottleneck, reuse data, and speed up computation. After implemented by using the FPGA card DE10-Pro, the FPGA-based sound field rendering systems outperform the software simulations carried out on a desktop machine with 512 GB DRAMs and a Xeon Gold 6212U processor running at 2.4 GHz by 11 times, 13 times, and 18 times in computing performance in the case of the 2nd-order, 4th-order, and 6th-order FDTD schemes, respectively.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#125] Midas: A System for Achieving "Golden" Reproducibility in HPC

• Authors: *Austin Minor (Virginia Tech), Wu-chun Feng (Virginia Tech)
• Abstract (click to expand):
  With the exponentially improving serial performance of CPUs from the 1980s and 1990s slowing to a standstill by the 2010s, the HPC community has seen parallel computing (via multi-core CPUs, many- core GPUs and TPUs, and even FPGAs) become ubiquitous, which, in turn, has led to a proliferation of parallel programming models, e.g., CUDA, OpenACC, OpenCL, and SYCL. This diversity in hard- ware platform and programming model has forced application users to port their codes from one hardware platform to another (e.g., CUDA on NVIDIA GPU to OpenCL on AMD GPU) and demonstrate reproducibility via ad-hoc unit testing. To more rigorously ensure reproducibility between codes, we propose Midas, a system to ensure that the results of the original code match the results of the ported code by leveraging the power of snapshots to capture the state of a system before and after the execution of a kernel.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#126] OpenACC Implementation of Radiative Transfer Simulation Code

• Authors: Ryohei Kobayashi (University of Tsukuba), Norihisa Fujita (University of Tsukuba), Yoshiki Yamaguchi (University of Tsukuba), Taisuke Boku (University of Tsukuba), Kohji Yoshikawa (University of Tsukuba), Makito Abe (University of Tsukuba), Masayuki Umemura (University of Tsukuba)
• Abstract (click to expand):
  Graphics processing units (GPUs) offer good peak performance and high memory bandwidth. They have been widely used in high-performance computing (HPC) systems as accelerators. However, they are not suitable for all applications, and there are applications where they don’t efficiently work on. One of such applications is multiphysics simulation. Multiphysics is defined as the coupled processes or systems involving more than one simultaneously occurring physical fields and the studies of and knowledge about these processes and systems. Therefore, multiphysics applications perform simulations with multiple interacting physical properties and there are various computations within a simulation, and GPU-non-suited ones can be included. Because of that, accelerating simulation speed by GPU only is quite difficult and this is why we try to combine GPU and FPGA and make the FPGA cover GPU-non suited computation. We call this concept Cooperative Heterogeneous Acceleration with Reconfigurable Multidevices (CHARM) and have been working on GPU-FPGA-accelerated computation for radiative transfer simulation in astrophysics as a proof of concept.
  We are currently working on a programming environment that enables to use both accelerators in a GPU-FPGA equipped HPC cluster system with OpenACC. In order to realize it, we investigate performance of OpenACC-based GPU implementation of the simulation code by comparing with those of OpenMP-based CPU implementation and CUDA-based GPU implementation, and confirmed that there is almost no difference between the CUDA and OpenACC implementations.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#127] Acoustic simulation using lattice Boltzmann method by multi-GPU parallel computing

• Authors: *Shota Suzuki (The University of Tokyo), Takashi Shimokawabe (The University of Tokyo)
• Abstract (click to expand):
  In recent years, the lattice Boltzmann method has attracted attention as a new method for acoustic analysis. The lattice Boltzmann method has been proposed as an analysis method for fluid dynamics, and it can be applied to acoustic analysis by using the acoustic time scale, which deal with the fast phenomenon of moving virtual particles. In addition, since the lattice Boltzmann method uses an orthogonal lattice, it is compatible with the immersed boundary method, which is used for complex or moving boundary. When performing acoustic analysis while taking into account the wave nature of sound, the resolution must be high, and a large computational domain must be prepared for this purpose. Therefore, in this study, we perform acoustic analysis using lattice Boltzmann method and immersed boundary method by multi-GPU parallel computing. The problem with using parallel computing here is the unbalance of the computational domains within each GPU. When the immersed boundary is biased to one part of the analysis domain, there is an imbalance in the computation speed within each GPU. In this poster, we will discuss the calculation speed of the immersed boundary method depending on the division method of the analysis domain.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#128] Smart In-Situ Visualization Framework on the Fugaku Environment

• Authors: *Ken Iwata (Kobe University), Go Tamura (Kobe University), Naohisa Sakamoto (RIKEN R-CCS), Jorji Nonaka (RIKEN R-CCS)
• Abstract (click to expand):
  Continuous increase in the simulation scale and the cost of I/O have increased the attention to the in-situ processing, where the simulation data is reduced in different manners for minimizing this I/O cost. However, traditional batch-based in-situ visualization can produce large amounts of rendering results for post-hoc visual analysis, which can make difficult to gain insight into the simulation results. In this poster, we present an in-situ visualization framework, named as "Smart In-Situ Visualization", which is focused not only on simple data reduction, but especially on the elimination of unnecessary timesteps and viewpoints for understanding the underlying simulation phenomena without missing important data features. For this purpose, we have worked on an in-situ adaptive timestep selection, and have also started working on an adaptive viewpoint selection to be used with the in-situ multiple viewpoint rendering. We expect that these features can be useful for reducing the I/O cost, and the time required to obtain scientific knowledge from the numerical simulation results.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#129] An FPGA Accelerator of Bayesian Network Structure Learning Using Parallel Calculation of Local Scores

• Authors: *Ryota Miyagi (Kyoto University), Hideki Takase (The University of Tokyo)
• Ryota Miyagi is the 2nd Prize winner of the HPC Asia 2022 Best Student Poster Award in Memory of Hiroshi Nakashima
• Abstract (click to expand):
  A Bayesian network (BN) is a probabilistic graphical model that encodes conditional independence relations among random variables to a directed acyclic graph (DAG). Using BN, we can efficiently estimate the posterior distribution from the given evidence. A dynamic programming method based on substructure scores called local scores can find the provable optimal DAG structure of a BN. However, the number of local scores is vast despite appropriate limitations, and thus the calculation is time-consuming. The research objective is accelerating optimal structure learning for large BNs using parallel calculation of local scores. The proposed FPGA accelerator extracts a high degree of data parallelism and pipeline parallelism with few memory resources by having parallel calculation modules according to the amount of FPGA resources and streaming the dataset stored in one place to each module. The proposed method calculates the local score up to 230 times faster and learns the optimal DAG structure 3.5 times faster, thus enabling calculations that are too time-consuming for software. Furthermore, a comparison of the accelerators proves that the performance improves as the FPGA resources increase. The proposed method is a scalable approach that promises to extract a high degree of parallelism even in an environment consisting of multiple FPGA resources, such as an FPGA cluster.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#130] RIKEN CGRA: Reconfigurable Data-Driven Architecture for Future HPC

• Authors: Boma Adhi (RIKEN Center for Computational Science), Carlos Cortes (RIKEN Center for Computational Science), Yiyu Tan (RIKEN Center for Computational Science), Takuya Kojima (The University of Tokyo), Artur Podobas (KTH Royal Institute of Technology), Kentaro Sano (RIKEN Center for Computational Science)
• Abstract (click to expand):
  CGRAs were traditionally used in embedded-devices to provide the CPU with extra computing power with low energy consumption. In order to understand how CGRA can be used in an HPC environment, we previously conducted a literature survey on CGRA and developed a framework for a design-space exploration of CGRAs in the HPC environment. Based on this result, we proposed a CGRA architecture which allows testing much larger CGRA or multiple CGRA islands running on an FPGA cluster connected to Fugaku supercomputer, enabling us to explore research questions such as the heterogeneous composition of tiles, their functionality, and the (inter-tile) connectivity; exploration of memory subsystem, such as, the design or the load-store unit, and how the load and store unit talks to multiple memory controllers.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#131] In-situ analysis with OpenMP task for leveraging unused core

• Authors: *Tatsuya Akazawa (The University of Tokyo), Toshihiro Hanawa (The University of Tokyo), Yohei Miki (The University of Tokyo)
• Abstract (click to expand):
  In recent years, the number of physical cores of the processor in HPC clusters has been increasing. However, the total performance might be reduced if all the cores are used. For this reason, there are cases where the number of cores used is intentionally limited to maximize the CPU's performance. The cores that are not being used then are called "unused cores." We plan to leverage the unused cores to support the main computation. Our goal is to create a framework that allows unused cores to support computation. The framework is expected to provide functions including auto-tuning dynamically and in-situ analysis and visualization technology. In this study, we aimed to demonstrate that OpenMP task pragma can be used to manage efficiently the main computation and analysis processes and reduce the execution time. For a code where the main computation and analysis were originally sequential processes, we applied parallelization using the OpenMP task and confirmed that the execution time was reduced.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#132] Offloading Integer GMRES Method to Accelerators

• Authors: *Yijie Yu (The University of Tokyo), Toshihiro Hanawa (The University of Tokyo)
• Abstract (click to expand):
  In many applications, efficiency does not necessarily raise with the increase of precision. Higher precision numbers may cause some problems, like over-allocation of bits resources will waste power, bandwidth, storage. In the HPC field, transprecision is a solution to the above problem, which uses different precision to execute computing. In order to test, an integer-based GMRES algorithm is verified. And the int-GMRES converts each FP into an integer by operand shift. In addition, as a kind of reconfigurable hardware, the FPGA accelerator provides the possibility of higher performance computing which can optimize arithmetic units and data types to suit the precision. The DPC++ compiler based on SYCL is a toolkit of oneAPI and broad heterogeneous support that includes GPU, CPU, and FPGA devices. DPC++ compiler supports shift left and shift right operators, which can help us convert fixed-point numbers into integers, submitting each kernel's actions into a queue and offloading it to the FPGA to complete the computing. The numerical results demonstrated that the int-GMRES solver had comparable solver performance in terms of convergence to the standard FP solver.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#133] In-situ performance profiling for leveraging the ''unused cores''

• Authors: *Tianya Wu (The University of Tokyo), Jun Kudo (The University of Tokyo), Toshihiro Hanawa (The University of Tokyo)
• Abstract (click to expand):
  In recent years, the number of physical cores built into CPUs has been increasing. However, for HPC cluster, simultaneously activating all cores for computation does not necessarily lead to maximum performance. Lack of parallelism, memory-bound constraints, as well as power and energy constraints are responsible for this phenomenon. To achieve maximum overall performance, a fraction of cores are expected to stay idle during the computation. These cores are usually called "unused cores", which can be further utilized for purpose other than computation. In this study, we proposed a framework that leverages the "unused cores" for profiling during the execution with low overhead.SystemTap can detect the entries and exits of specific functions in the main computation and invoke the related handlers. The handlers using PAPI can extract information from the performance counters for profiling. Based on the result of profiling, factors that hinder the speedup of computation can be inferred. Subsequently, the corresponding optimization processing can be inserted.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#134] Cascadic Parareal Method for Explicit Time-Marching Schemes

• Authors: *Yen-Chen Chen (The University of Tokyo), Kengo Nakajima (The University of Tokyo)
• Yen-Chen Chen is the 3rd Prize winner of the HPC Asia 2022 Best Student Poster Award in Memory of Hiroshi Nakashima
• Abstract (click to expand):
  Nowadays, conventional High-Performance Computing (HPC) methods for PDE equations numerical solvers are reaching their limits. As we move toward the exaflops supercomputing era, numerical PDE solvers parallelization reaches its saturation point in the spatial dimension and is restricted by the time domain instead. This leads to the development of parallel-in-time methods. Various parallel-in-time methods have been studied since the year 1964. Well-known methods such as parareal and multigrid reduction in time (MGRIT) have been shown to provide reasonable acceleration to partial differential equations (PDE) implicit schemes. However, only a few have applied pure explicit schemes. This research introduces a parallel-in-time method optimized for explicit schemes. The proposed method constructs a multiple coarsening layer structure and solves the parareal algorithm through coarse to fine layers. Furthermore, the relaxation method is defined to solve across the whole time segment divided by the number of processors. This way improves the efficiency of parallel-in-time solvers with a limited amount of processors. This research conducts numerical experiments for a one-dimensional advection equation and a two-dimensional simulation of compressible viscous flow around a circular cylinder, using explicit time-marching schemes as relaxation methods. The research result shows that the proposed parallel-in-time method could improve the computation efficiency of explicit solvers compared to pure spatial parallelization. Furthermore, we are working on applying adaptive mesh refinement to extend the two-dimensional result for supersonic flow with shock wave appearances.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)

[#135] THINK GREEN! Energy Efficient Cloud for HPC

• Author: Madhu Thorat (IBM)
• Abstract (click to expand):
  Today large, complex simulations and heavy workloads can run in the cloud with High Performance Computing (HPC) products and services. In the past decade adaptation of Cloud for HPC has increased significantly, so energy consumption has also increased due to the exponential rise of Cloud data centers and other infrastructure. This has led to two big problems: 1) It has resulted in substantial rise in carbon emissions in the environment. 2) Cloud infrastructure may be utilizing high amount of energy and this may cost a fortune to the Cloud providers. These problems have made it necessary to follow energy efficient solutions for Cloud infrastructure for HPC environments, which will help to reduce energy consumption. Such solutions would be beneficial for both the environment and cloud infrastructure. The poster will give information about the Energy Efficient Cloud Approaches which can help to achieve the goal of going green for Cloud Infrastructure for HPC.
• 1-page extended abstract (PDF file)
• Poster or slides (PDF file)